Verilog HDL Advanced - This instructor-led class is taught in a virtual classroom over 2 half days of instruction. To perform the lab exercises, you will connect to a remote computer provided by Altera® FPGA Training and pre-configured with all the necessary tools. Information required to connect to the remote system will be provided during the class. No setup is needed. Course Description You will learn efficient coding techniques for writing synthesizable Verilog for Altera® FPGAs and CPLDs. You will gain experience in behavioral and structural coding while learning how to effectively write common logic functions including registers, memory, and arithmetic functions. You will learn how to parameterize your Verilog design, increasing flexibility and reusability. You will be introduced to testbenches and the constructs used when building them. The exercises will use the Quartus Prime software for synthesis and the Questa*-Altera® FPGA Edition software for simulation. Note: While the course focuses on the Quartus® Prime software, many concepts can be used with other synthesis tools. *Other names and brands may be claimed as the property of others. Course Objectives At course completion, you will be able to: Implement synthesizable sequential and combinatorial RTL code Design finite state machines using multiple encoding schemes Develop simple testbenches for verification Use tools in the Quartus Prime software to synthesize code and verify results Run functional simulations in the Questa*-Altera® FPGA Edition software Skills Required Completion of the "Introduction to Verilog HDL" course or some prior knowledge and use of Verilog hardware description language (HDL) Background in digital logic design Understanding of synthesis and simulation processes If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_IHDL230. FPGA_IHDL230. <p>Verilog HDL Advanced</p>