SOC-11 - RTOS Development on Altera® SoC Platforms - 2 Days - Enroll Now This course is built for Altera® SoC FPGA designers who want to develop deterministic, production grade real time systems using Zephyr RTOS on Altera SoC FPGA platforms. The course focuses on real world Zephyr practices for HPS + FPGA systems: board/BSP bring-up, Zephyr device tree and driver model, interrupt and scheduling determinism, DMA and cache/coherency correctness, and robust integration of custom FPGA IP via HPS to FPGA bridges. Rather than teaching RTOS basics, the course concentrates on what typically blocks successful deployments: priority inversion, ISR overload, race conditions, timing jitter, non-coherent DMA corruption, device tree mismatches, and integration failures across HPS (software) and FPGA fabric (hardware). The end goal is a repeatable methodology to ship an RTOS based SoC FPGA product with measurable real time performance. Course Content: 1. Altera SoC HPS Architecture Overview 2. HPS–FPGA Bridge Architecture (AXI, Lightweight AXI, F2H) 3. Zephyr RTOS Project Structure & Build System (west, CMake, Kconfig) 4. Board Support Package (BSP) Bring-Up for Altera SoC Targets 5. Zephyr Device Tree Fundamentals & Overlay Workflow 6. Zephyr Kernel Scheduler — Preemption, Priorities & Time Slicing 7. Interrupt Handling, IRQ Routing on HPS, and ISR Design Rules 8. Zephyr Device Driver Model — APIs, Instance Based Config, Shell 9. Synchronisation Primitives — Semaphores, Mutexes, Message Queues 10. Priority Inversion, Deadlocks & the Priority Inheritance Protocol 11. FPGA Manager & Partial Reconfiguration Workflow Under Zephyr 12. HPS–FPGA Memory Mapped I/O — Address Maps, Bridges & BAR Sizing 13. Writing Production Zephyr Drivers for Custom FPGA IP (PIO, FIFO, DMA IP) 14. Shared Memory, Mailbox & Messaging Patterns Across HPS and FPGA 15. Device Tree Bindings for Custom FPGA IP 16. Altera HPS DMA Controller Architecture & Zephyr DMA API 17. Cache Coherency in HPS+FPGA Systems — L2 Flush, Invalidation & ACP 18. Non-Coherent DMA Pitfalls & Corruption Patterns 19. Achieving Timing Determinism — Tickless Mode, Deadline Scheduling & IRQ Affinity 20. Profiling & Tracing Real Time Performance with Zephyr Tracing & SystemView 21. Watchdog Timers, Fault Handling & Panic Dumps in Zephyr 22. Power Management — CPU Idle, Clock Gating & Wake Sources on HPS 23. Security Hardening — Secure Boot, TrustZone Partitioning & Zephyr Isolation 24. Board Level Checklist & Root Cause Methodology 25. Shipping Checklist — Real Time Validation, CI/CD Integration & Regression Testing Prerequisites: - Proficiency in C programming (pointers, structs, function pointers, volatile) - Familiarity with ARM Cortex A or Cortex M architecture concepts (registers, exceptions, privilege levels) - Basic FPGA design experience — ability to compile and load a Quartus® project - Comfort with the Linux command line (file system, bash scripts, package management) - Basic understanding of bus/memory mapped I/O concepts (address maps, read/write registers) Recommended: - Prior exposure to any RTOS (FreeRTOS, ThreadX, or similar) at the task/semaphore level - Familiarity with Altera HPS–FPGA bridge architecture (from Altera SoC FPGA Embedded Design course) - Experience with JTAG debugging tools (J-Link, Lauterbach, or OpenOCD) - Basic knowledge of AXI bus protocol and memory coherency concepts - Exposure to device tree syntax (Linux DTS/DTSI format) Tools Required: - Altera® Quartus® Prime Pro - Ashling RiscFree IDE for Altera FPGA - ModelSim-Altera FPGA Edition - System Console / Signal Tap II - Zephyr SDK & west - Python - Device Tree Compiler (dtc) - SEGGER J-Link / J-Trace - OpenOCD -SEGGER SystemView / Percepio Tracealyzer - minicom / PuTTY - Lauterbach TRACE32 (optional) Course code: SOC-11. FA_RTOS.