RapidIO IP Core User Guide Lists Wrong TOP_LEVEL_NAME for ModelSim Simulation of Non-Arria 10 IP Core Variations - RapidIO IP Core User Guide Lists Wrong TOP_LEVEL_NAME for ModelSim Simulation of Non-Arria 10 IP Core Variations Description The name of the RapidIO IP core top-level file for simulation in the ModelSim simulator changed in the IP core v14.1 and later, for simulation of IP core variations that target a non-Arria 10 device. The user guide lists the filename tb . However, the correct filename, starting in IP core version 14.1, is rapidio_0.tb . The RapidIO MegaCore Function User Guide is not updated with this change. For a similar issue with Arria 10 variations, refer to RapidIO Core User Guide Lists Wrong TOP_LEVEL_NAME for ModelSim Simulation of Arria 10 IP Core Variations . For a related issue for non-Arria 10 variations, refer to RapidIO IP Core User Guide Lists Outdated Instructions for Simulation of Non-Arria 10 IP Core Variations . Resolution Ensure that you simulate your non-Arria 10 RapidIO IP core in the ModelSim simulator with TOP_LEVEL_NAME set to rapidio_0.tb . For non-Arria 10 variations of the IP core, replace the simulation instruction set TOP_LEVEL_NAME tb with the new simulation instruction set TOP_LEVEL_NAME rapidio_0.tb This issue will be fixed in a future version of the RapidIO MegaCore Function User Guide . Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 14.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']