What is the maximum payload size supported in Stratix V Hard IP for PCI Express? - What is the maximum payload size supported in Stratix V Hard IP for PCI Express? Description Due to a documentation error, the table Dynamically Reconfigurable Registers in the Hard IP Implementation of the Stratix® V Hard IP for PCI Express® User Guide shows a 4096 byte maximum payload while other tables show 2048 bytes as the maximum. Resolution The correct maximum payload size is 2048 bytes. This will be corrected in a future version of the User Guide. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']