Why does the design example simulation in NCSim or Xcelium fail for the Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP core variant when selecting the “Enable RS-FEC” or “Enable Dynamic RS-FEC” options? - Why does the design example simulation in NCSim or Xcelium fail for the Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP core variant when selecting the “Enable RS-FEC” or “Enable Dynamic RS-FEC” options? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 18.1 and earlier, the design example's simulation for the Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP core variant with the “Enable RS-FEC” or “Enable Dynamic RS-FEC” options selected will fail in NCSim or Xcelium. This failure will typically take the form: *F,NOSNAP: Snapshot 'basic_avl_tb_top' does not exist in the libraries. Resolution To work around this issue, do not select either the Enable RS-FEC or Enable Dynamic RS-FEC options in the IP’s parameter editor when generating the design example for simulation in NCSim or Xcelium. Custom Fields values: ['novalue'] Troubleshooting 2205694248 True ['Low Latency 100G Ethernet IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 18.1 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']