Why is the latency of my DSP block incorrect? - Why is the latency of my DSP block incorrect? Description Due to a problem in the Quartus® II software version 13.0 SP1, you may see this problem if you synthesize your design using a 3rd party synthesis tool and use the DSP input registers. Resolution To work around this problem, download and install patch 1.dp5n from the links below. You must install the Quartus II software version 13.0 SP1 before installing this patch. Download the version 13.0 SP1 patch 1.dp5n for Windows (.exe) Download the version 13.0 SP1 patch 1.dp5n for Linux (.run) Download the Readme for the Quartus II software version 13.0 SP1 patch 1.dp5n (.txt) This problem is scheduled to be fixed in a future release of the Quartus II software. Custom Fields values: ['novalue'] Troubleshooting novalue False ['DSP'] ['FPGA Dev Tools Quartus II Software'] novalue 13.0.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']