Why doesn't the Quartus II software correctly synthesize signed packed array variables in SystemVerilog? - Why doesn't the Quartus II software correctly synthesize signed packed array variables in SystemVerilog? Description Due to a problem in the Quartus® II software, signed packed array variables in SystemVerilog may not be synthesized correctly. This problem may occur when assigning a one-dimensional array variable to a signed packed array variable if the index range is not explicitly specified. For example, the following code may be synthesized incorrectly by the Quartus II software: logic clk; logic signed [3:0][31:0] packed_array_variable; logic signed [31:0] array_variable; always_ff @ (posedge clk) packed_array_variable[0] <= array_variable; Resolution To work around this problem, explicitly declare the index range when assigning a one-dimensional array variable to a packed array variable. For example, in the above code, change the last line to: packed_array_variable[0][31:0] <= array_variable; Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 6.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']