Why does my Intel® Stratix® 10 FPGA L-tile simplex receiver have low jitter tolerance when no transmitter is used for that channel? - Why does my Intel® Stratix® 10 FPGA L-tile simplex receiver have low jitter tolerance when no transmitter is used for that channel? Description Due to a problem in the Intel® Quartus® Prime Software version 16.1.2 ES Edition and earlier calibration code, your Intel Intel® Stratix® 10 device simplex receiver may have low jitter tolerance when no transmitter is used in that channel. Resolution To work around this problem, you can instantiate a simplex TX transceiver and merge it into the same channel as the simplex RX transceiver. After calibration is complete, you can write a 1'b0 to address offset 0x10F to stop the TX serializer clock from toggling and save power. If user-mode recalibration must be run again, you must first turn the TX serializer back on by writing a 1'b1 to address offset 0x10F. Custom Fields values: ['novalue'] Troubleshooting FB: 406016 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Standard'] 16.1.2 16.1.2 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']