SOPC Builder cannot recognize System Verilog files for UNiPHY-based memory controllers - SOPC Builder cannot recognize System Verilog files for UNiPHY-based memory controllers
Description For all UniPHY-based memory controllers and the Traffic Generator, SOPC Builder cannot recognize System Verilog files. As a result, System Verilog files are not automatically compiled during ModelSim simulation. Resolution Manually compile all System Verilog files in ModelSim before using the simulation flow.
Custom Fields values:
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Troubleshooting
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True
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['FPGA Dev Tools Quartus II Software']
10.0
10.0
['Programmable Logic Devices']
['novalue']
['novalue']
['novalue'] - 2021-08-25
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