Why does ASx4 configuration fail for Intel® Stratix® 10 devices when using OSC_CLK_1 as the configuration clock source? - Why does ASx4 configuration fail for Intel® Stratix® 10 devices when using OSC_CLK_1 as the configuration clock source? Description Due to a known problem in Intel® Quartus® Prime Pro Edition software version 20.3 and earlier, ASx4 configuration of Intel® Stratix® 10 devices may fail intermittently when OSC_CLK_1 is used as configuration clock source. For all Intel® Stratix® 10 devices AS_CLK is 125MHz For Intel® Stratix® 10 GX040, Intel® Stratix® 10 SX040, and Intel® Stratix® 10 TX040 devices only, AS_CLK is 125MHz, or 133MHz Resolution As a workaround, avoid the combinations stated in the description. This problem is fixed starting with the Intel® Quartus® Prime Pro Edition software version 21.1. Custom Fields values: ['novalue'] Troubleshooting 1508029570 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.1 20.2 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']