How do I resolve timing failures on the Stratix V GX Reconfiguration Controller IP pmatestbussel bus when I recompile my design in Quartus II software version 13.0? - How do I resolve timing failures on the Stratix V GX Reconfiguration Controller IP pmatestbussel bus when I recompile my design in Quartus II software version 13.0? Description To resolve timing failures reported on the pmatestbussel bus when compiling your design in Quartus II software version 13.0, you should follow these steps: Regenerate the Transceiver Reconfiguration Controller IP in Quartus 13.0. Verify the top level 'derive_pll_clocks' SDC command is executed before sourcing the alt_xcvr_reconfig.sdc file. If the Transceiver TX PLL is instantiated as an external Tx PLL, replace the following constraint in the alt_xcvr_reconfig.sdc file. Replace set_clock_groups -asynchronous -group [get_clocks {*xcvr_native*avmm*pmatestbussel[0]}] With set_clock_groups -asynchronous -group [get_clocks {*hssi_avmm_interface_inst|pmatestbussel[0]}] Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 13.0 ['Arria® V GZ FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']