Why do I have hardware failures in IO registers with a locally routed clock? - Why do I have hardware failures in IO registers with a locally routed clock? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.3 and later, you may see functional errors in an IO register that has a locally routed clock. The functional failures occur because the clock route is illegal and not analyzed for timing. This problem only affects Intel Agilex® devices where there is a register in an IO cell whose clock is routed on local routing rather than a global clock net. Resolution To work around this problem, either ensure that the clock is routed on a global clock net or that register is not in an IO cell. Beginning with the Intel® Quartus® Prime Pro Edition Software version 22.1, designs constrained to implement a register in an IO cell with a locally routed clock will error out. Patches are scheduled to be released that will add this error to previous versions. Custom Fields values: ['novalue'] Troubleshooting 14015733446 14015359810 True ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.1 21.3 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']