Why is the F2SDRAM bridge unstable, or unable to perform read/write transactions after performing a core.rbf full configuration through FPGA overlay in Linux? - Why is the F2SDRAM bridge unstable, or unable to perform read/write transactions after performing a core.rbf full configuration through FPGA overlay in Linux? Description Due to a problem in the bridge driver for the F2SDRAM bridge the following behaviour may be seen: - A lockup condition in the F2SDRAM bridge when You perform a full FPGA core configuration in Linux through an FPGA overlay. You disable the bridge in the U-Boot console after a core.rbf configuration by running the “disable bridge” command. - A Linux kernel exception (data abort) or a non-completed F2SDRAM transaction after FPGA Core Re-Configuration You perform a full FPGA core configuration in Linux through an FPGA overlay An Arm AXI Controller issues transactions to the HPS via the F2SDRAM bridge You perform a full FPGA core re-configuration in Linux through an FPGA overlay An Arm AXI Controller issues transactions to the HPS via the F2SDRAM bridge Linux Kernel Exception : Null Pointer Exception maybe seen, or the Arm AMBA AXI Ready signsl from the FPGA2SDRAM bridge may go inactive before the first transaction completes These problem does not affect the H2F or Lightweight H2F bridge. These problem impacts Intel Agilex® 7 SoC, Intel® Stratix® 10 FPGA and Intel® eASIC™ N5X devices. Resolution The problem has been fixed with the latest GitHub arm-trusted-firmware version socfpga_v2.7.1 and v2.8.0 and U-Boot version socfpga_v2022.10. For the ATF flow, the patch is available in the arm-trusted-firmware version socfpga_v2.7.1 and v2.8.0 - https://github.com/altera-opensource/arm-trusted-firmware Patch commit ID: v2.7.1 = https://github.com/altera-opensource/arm-trusted-firmware/commit/0a5edaed853e0dc1e687706ccace8e844b2a8db7 v2.8.0 = https://github.com/altera-opensource/arm-trusted-firmware/commit/bf933536d4582d63d0e29434e807a641941f3937 For legacy (Non-ATF) flow – the patch is available in u-boot-socfpga - socfpga_v2022.10 - https://github.com/altera-opensource/u-boot-socfpga/tree/socfpga_v2022.10 Patch commit ID: https://github.com/altera-opensource/u-boot-socfpga/tree/61ae22e548ebda525d5216d107e45f20eca70537 https://github.com/altera-opensource/u-boot-socfpga/tree/1dda7c081ee51d6c4b52d2ef773464b745fb9ec0 https://github.com/altera-opensource/u-boot-socfpga/tree/66f3f251b2d5767c2c4abd85e01df415e6c5bfe7 https://github.com/altera-opensource/u-boot-socfpga/tree/45a62a422a3db7fcf0636e4ad95e12354e719189 https://github.com/altera-opensource/u-boot-socfpga/tree/775e01b091c58f6d4d6551ef2f194d8b6c0ca8bb https://github.com/altera-opensource/u-boot-socfpga/tree/e870a2ee57e102de19f9f0283033b3336a54f8a3 Alternatively, you may use the following approach to avoid the F2SDRAM bridge lockup problem: Avoid using the FPGA overlay for full configuration. Do not perform a bridge disable in the U-Boot stage. Custom Fields values: ['novalue'] Troubleshooting 15012815731 ,18018343176 False ['novalue'] ['novalue'] novalue novalue ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']