FIR Coefficient Reload May Get Delayed - FIR Coefficient Reload May Get Delayed Description FIR Compiler II intermittently inserts unnecessary delay registers between a coefficient storage register and the multiplier that uses that coefficient. This issue may cause the first FIR iteration after a coefficient update or reset to be calculated using the wrong values. Once the correct coefficient value propagates through the delay registers, subsequent FIR iterations will be calculated correctly. This issue affects FIRs that use reloadable coefficients. FIRs that use constant coefficients are not affected. This issue is fixed in version 12.0 of the FIR Compiler II MegaCore function. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 12.0 11.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']