Why are the timing margins the same values for all corners when performing Report DDR in the Timing Analyzer for Intel® Arria® 10 FPGA external memory interfaces? - Why are the timing margins the same values for all corners when performing Report DDR in the Timing Analyzer for Intel® Arria® 10 FPGA external memory interfaces? Description The I/O timing, which includes Address/Command, DQS gating, read capture, write and write levelling is fully calibrated over process, voltage, and temperature (PVT). Therefore, the margins are the same across all models. The Report DDR in the Timing Analyzer reports the worst case values over all corners for these calibrated interfaces. Resolution N/A Custom Fields values: ['novalue'] Troubleshooting - False ['novalue'] ['novalue'] novalue novalue ['Arria® 10 GT FPGA', 'Arria® 10 GX FPGA', 'Arria® 10 SX FPGA'] ['novalue'] ['novalue'] ['novalue']