Why do I see an IOPLL not achieving lock in HPS first mode on Stratix® 10 SoC FPGAs ? - Why do I see an IOPLL not achieving lock in HPS first mode on Stratix® 10 SoC FPGAs ? Description Due to a problem in Secure Device Manager (SDM) fimrware of Quartus® Prime Pro Edition Software version 24.1 and eariler, you may see IOPLL's lock signal failing to go HIGH after the FPGA is configured by the Hard processor System (HPS) in HPS first mode when using Stratix® 10 SoC FPGAs. Resolution This problem is scheduled to be fixed in a future release of Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 18038274303 True ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 21.4 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']