Critical Warning(16643): Found INPUT_TERMINATION assignments found for "ref_clk" pin with multiple values. Using value: "OFF" - Critical Warning(16643): Found INPUT_TERMINATION assignments found for "ref_clk" pin with multiple values. Using value: "OFF" Description Due to a problem with the Intel® Quartus® Prime Pro version 19.1, you may encounter the above critical warning when using the Triple-Speed Ethernet Intel® FPGA IP with LVDS I/O design when the default input termination of LVDS reference clock is overridden by using the following QSF assignment or through the assignment editor. set_instance_assignment -name INPUT_TERMINATION OFF -to ref_clk Resolution To work around this problem, remove the following line from the QIP file of the Triple-Speed Ethernet Intel® FPGA IP when there is a need to override the default input termination of the LVDS reference clock setting. set_instance_assignment -entity "" -library "altera_lvds_core14_191" -name INPUT_TERMINATION DIFFERENTIAL -to inclock Custom Fields values: ['novalue'] Troubleshooting 1507223442 False ['Triple-Speed Ethernet IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 19.1 ['Arria® 10 GT FPGA', 'Arria® 10 GX FPGA', 'Arria® 10 SX FPGA', 'Cyclone® 10 GX FPGA', 'Cyclone® 10 LP FPGA', 'Stratix® 10 DX FPGA', 'Stratix® 10 GX FPGA', 'Stratix® 10 MX FPGA', 'Stratix® 10 SX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']