Why do I get inconsistent readings during readback from the IO column delay register in External Memory Interfaces Intel® Arria® 10 FPGA IP via On-Chip Debug Port? - Why do I get inconsistent readings during readback from the IO column delay register in External Memory Interfaces Intel® Arria® 10 FPGA IP via On-Chip Debug Port? Description When reading a value from the IO column pin delay register of External Memory Interfaces Intel® Arria® 10 FPGA IP via On-Chip Debug Port you may get a different value once in a few hundred reads. Resolution Experimental data shows that incorrect values may occur for up to 2% of reads in the whole span of environmental conditions. The workaround to this is to read the register N times and only trust the value if all N samples match - if there's a mismatch you should repeat another round of reads. The value of N should be according to the assumed reliability of the read. Custom Fields values: ['novalue'] Troubleshooting 18024207101 False ['External Memory Interfaces Arria® 10 FPGA IP'] ['novalue'] novalue novalue ['Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']