DisplayPort IP Support Center - The DisplayPort IP Support Center provides information on how to select, design, and implement DisplayPort IPs. Information on how to select, design, and implement DisplayPort IPs. Design Pages {"title":"DisplayPort IP Support Center"} The DisplayPort IP Support Center is organized into industry-standard stages, which provides you with various resources to plan, select, design, implement, and verify your DisplayPort IP cores for Agilex™ 7, Agilex™ 5, Agilex™ 3, Stratix® 10, Arria® 10, and Cyclone® 10 devices. There are also guidelines on how to bring up your system and debug the DisplayPort links. This page is organized into categories that align with a DisplayPort system design flow from start to finish. Get additional support for Agilex™ 7 FPGA Interface Protocol Design , Agilex™ 5 FPGA Interface Protocol Design and Agilex™ 3 FPGA Interface Protocol Design step-by-step guided journeys for standard development flows surfacing the key critical resources and documentation. For other devices, search the Device and Product Support Collections . Getting Started Getting Started 1. Device and IP Selection What features are supported in the DisplayPort IP? 1. Device and IP Selection Feature Description DisplayPort IP Core Features Conforms to the Video Electronics Standards Association (VESA) DisplayPort Standard version 2.0 Scalable main data link 1, 2, or 4 lane operation 1.62, 2.7, 5.4, 8.1, and 10.0 gigabits per second (Gbps) per lane with an embedded clock (1)(2) Color support RGB 18, 24, 30, 36, or 48 bpp YCbCr 4:4:4 24, 30, 36, or 48 bpp YCbCr 4:2:2 16, 20, 24, or 32 bpp YCbCr 4:2:0 12, 15, 18, or 24 bpp 8B/10B Channel Coding supports 40-bit (quad symbol) and 20-bit (dual symbol) transceiver data interface 128B/132B Channel Coding supports 32-bit transceiver data interface Support for 1, 2, or 4 parallel pixels per clock Support for 2 or 8 audio channels 8B/10B Channel Coding supports Multi-stream transport (MST) Arria® 10 devices support up to 4 streams Cyclone® 10 GX devices support up to 4 streams 128B/132B Channel Coding supports up to 4 streams 8B/10B Channel Coding supports progressive and interlaced video 128B/132B Channel Coding supports progressive video Source support for proprietary video image format (optional) Support for sink non-GPU mode Support for adaptive sync feature Support for High Dynamic Range (HDR) metadata transport using secondary stream data packet Auxiliary channel for 2-way communication (link and device management) Hot plug detect (HPD) Sink announces its presence Sink requests the source’s attention 8B/10B Channel Coding in SST mode supports the High-bandwidth Digital Content Protection (HDCP) feature for Arria® 10 and Stratix® 10 devices Source support for proprietary video image format (optional) Source and sink support for AXIS video format (optional) Typical Application Interfaces within a PC or monitor External display connections, including interfaces between a PC and monitor or projector, between a PC and TV, or between a device such as a DVD player and TV display Device Family Support Agilex™ 7 (F-tile), Stratix® 10 (H-tile and L-tile), Arria® 10, Cyclone® 10 GX, Arria® V, Cyclone® V, and Stratix® V FPGA devices. Design Tools IP Catalog in the Quartus® Prime software for IP design instantiation and compilation Timing Analyzer in the Quartus® Prime software for timing analysis Questa*-Altera® FPGA Edition, ModelSim* -Altera® FPGA Edition, NCSim, VCS*/VCS MX, and Xcelium* Parallel software for design simulation Note: The High-bandwidth Digital Content Protection (HDCP) feature is not included in the Quartus® Prime Pro Edition software. For more information refer to Interface Protocols IP Cores . Which FPGA Device Family Should I Use? Link Rate Supported by Device Family The table below shows the resource information for Arria® V and Cyclone® V devices using M10K; Arria® 10, Stratix® 10, and Stratix® V devices using M20K. The resources were obtained using the following parameter settings: Mode = simplex Maximum lane count = 4 lanes Maximum video input color depth = 8 bits per color (bpc) Pixel input mode = 1 pixel per clock Device Family Dual Symbol (20 Bit Mode) Quad Symbol (40 Bit Mode) FPGA Fabric Speed Grade Agilex™ 7 (F-tile) RBR, HBR, HBR2 RBR, HBR, HBR2, HBR3, UHBR10 1, 2, 3* Stratix® 10 (H-tile) RBR, HBR, HBR2 RBR, HBR, HBR2, HBR3, UHBR10, UHBR20 (Preliminary support only) 1, 2, 3* Stratix® 10 (L-tile) RBR, HBR, HBR2 RBR, HBR, HBR2, HBR3 1, 2, 3* Arria® 10 RBR, HBR, HBR2 RBR, HBR, HBR2, HBR3 1, 2 Cyclone® 10 GX RBR, HBR, HBR2 RBR, HBR, HBR2, HBR3 5, 6 Stratix ® V RBR, HBR, HBR2 RBR, HBR, HBR2 1, 2, 3 Arria ® V GX/GT/GS RBR, HBR RBR, HBR, HBR2 3, 4, 5 Arria® V GZ RBR, HBR, HBR2 RBR, HBR, HBR2 Any supported speed grade Cyclone ® V RBR, HBR RBR, HBR Any supported speed grade Note : Conditional support for Agilex™ 7, Arria® 10 and Stratix® 10 FPGA Fabric Speed Grade 3. Contact your Altera sales representative for more information. What is the DisplayPort FPGA IP Core FPGA Resource Utilization? Performance and Resource Utilization The resource utilization data indicates typical expected performance for the DisplayPort FPGA IP. The below table lists the resources and expected performance for selected variations. The results were obtained using the Quartus® Prime Pro Edition software version 20.2 for the following devices: Agilex™ F-tile (AGIB027R31B1E2VR0) Stratix® 10 (1SG280HU1F50E2VGS1) Arria® 10 (10AX115S2F45I1SG) Cyclone® 10 GX (10CX220YF780E5G) DisplayPort 1.4 FPGA IP Resource Utilization The table below shows the resource information for Agilex™ 7, Arria® 10, Cyclone® 10 GX, and Stratix® 10 devices using M20K. The resources were obtained using the following parameter settings: Mode = simplex Maximum lane count = 4 lanes Maximum video input color depth = 8 bits per color (bpc) Pixel input mode = 1 pixel per clock, 4 pixel per clock for Agilex™ 7 Device Streams Direction Symbol per Clock ALMs Logic Registers Primary Logic Registers Secondary Memory Bits Memory M10K or M20K Agilex™ 7 SST RX Quad 7040 11781 - 18368 18 SST TX Quad 7600 10149 - 26576 29 Stratix® 10 SST (Single Stream) RX Dual 5,200 7,700 640 16,256 11 SST (Single Stream) RX Quad 7,100 9,500 880 18,816 14 SST (Single Stream) TX Dual 5,100 7,100 420 12,176 15 SST (Single Stream) TX Quad 7,100 9,200 550 22,688 29 Arria® 10 SST (Single Stream) RX Dual 4,200 6,900 1,200 16,256 11 SST (Single Stream) RX Quad 6,000 8,800 1,600 18,816 14 SST (Single Stream) TX Dual 4,700 6,300 1,000 6,728 6 SST (Single Stream) TX Quad 6,700 8,400 1,200 16,520 13 MST RX Quad 20,100 24,400 4,500 58,368 32 (4 Streams) TX Quad 26,400 29,000 4,300 21,728 34 Cyclone® 10 GX SST (Single Stream) RX Dual 4,200 7,000 1,200 16,256 11 SST (Single Stream) RX Quad 6,000 8,800 1,600 18,816 14 SST (Single Stream) TX Dual 4,600 6,200 1,000 10,568 8 SST (Single Stream) TX Quad 6,800 8,400 1,200 17,096 13 MST RX Dual 22,000 24,400 4,400 58,368 32 (4 Streams) TX Quad 26,500 29,000 4,400 36,576 32 DisplayPort 2.0 FPGA IP Resource Utilization The table below shows the resource information for Stratix® 10 devices using the M20K. The resource count for the DP2.0 includes the resource count for the DP1.4 as well. The resources were obtained using the following parameter settings: Mode = simplex Maximum lane count = 4 lanes Maximum video input color depth = 8 bits per color (bpc) Pixel input mode = 4 pixel per clock Device Streams Direction Symbol per Clock ALMs Logic Registers Primary Logic Registers Secondary Memory Bits Memory M10K or M20K Stratix® 10 MST (1 Stream) RX - 21,500 38,000 - 244,352 74 MST (1 Stream) TX - 32,500 43,000 - 265,232 154 MST (4 Streams) RX - 48,000 70,751 - 357,632 164 MST (4 Streams) TX - 104,000 125,478 - 535,808 572 HDCP Resource Utilization The table lists the HDCP resource data for DisplayPort FPGA IP with configurations of SST (single stream) and at maximum lane of 4 configuration for Arria® 10 and Stratix® 10 devices. Device HDCP IP Support HDCP Key Management Symbols per Clock ALMs Combinatorial ALUTs Logic Registers Memory M20K DSP Stratix® 10 HDCP 2.3 TX 0 Dual 7,723 11,555 13,685 10 3 HDCP 2.3 TX 0 Quad 10,767 17,154 17,842 10 3 HDCP 2.3 TX 1 Dual 8,232 12,376 14,123 12 3 HDCP 2.3 TX 1 Quad 11,082 17,741 18,125 12 3 HDCP 2.3 RX 0 Dual 8,431 12,626 14,647 11 3 HDCP 2.3 RX 0 Quad 11,304 18,071 18,586 11 3 HDCP 2.3 RX 1 Dual 8,796 13,174 14,707 13 3 HDCP 2.3 RX 1 Quad 11,690 18,658 18,847 13 3 HDCP 1.3 TX 0 Dual 3,154 4,108 5,181 2 0 HDCP 1.3 TX 0 Quad 4,794 6,194 7,640 2 0 HDCP 1.3 TX 1 Dual 3,614 4,894 5,916 4 0 HDCP 1.3 TX 1 Quad 5,169 6,979 6,791 4 0 HDCP 1.3 RX 0 Dual 2,602 3,355 4,245 3 0 HDCP 1.3 RX 0 Quad 4,229 5,428 6,452 3 0 HDCP 1.3 RX 1 Dual 3,045 4,022 4,904 5 0 HDCP 1.3 RX 1 Quad 4,656 6,173 5,773 5 0 Arria® 10 HDCP 2.3 TX 0 Dual 6,752 10,724 13,138 10 3 HDCP 2.3 TX 0 Quad 9,934 16,760 16,716 10 3 HDCP 2.3 TX 1 Dual 7,165 11,350 13,615 12 3 HDCP 2.3 TX 1 Quad 10,374 17,364 17,561 12 3 HDCP 2.3 RX 0 Dual 7,395 11,721 13,775 11 3 HDCP 2.3 RX 0 Quad 10,547 17,674 17,335 11 3 HDCP 2.3 RX 1 Dual 7,785 12,420 14,213 13 3 HDCP 2.3 RX 1 Quad 10,972 18,424 18,167 13 3 HDCP 1.3 TX 0 Dual 2,505 3,826 5,336 2 0 HDCP 1.3 TX 0 Quad 3,724 5,648 5,882 2 0 HDCP 1.3 TX 1 Dual 2,849 4,429 5,846 4 0 HDCP 1.3 TX 1 Quad 4,142 6,335 6,635 4 0 HDCP 1.3 RX 0 Dual 1,995 2,879 4,248 3 0 HDCP 1.3 RX 0 Quad 3,270 4,810 4,851 3 0 HDCP 1.3 RX 1 Dual 2,382 3,549 4,821 5 0 HDCP 1.3 RX 1 Quad 3,677 5,472 5,604 5 0 2. Design Flow and IP Integration What is the DisplayPort related information and documentation available? Agilex™ 7 (F-tile), Stratix® 10 (H-tile and L-tile), Arria® 10, Cyclone® 10 GX, Arria® V GX/GT/GS, Arria® V GZ, Cyclone® V, Stratix® V DisplayPort FPGA IP User Guide How do I generate the DisplayPort IP core? Steps to generate DisplayPort IP Core in the Quartus® Prime software can be found in the chapter for Specifying IP Parameters and Options. DisplayPort FPGA IP User Guide DisplayPort FPGA IP Design Example User Guide: Agilex™ 5 FPGAs What is supported in the Quartus® generated DisplayPort design example? The DisplayPort FPGA IP core design examples demonstrate parallel loopback from DisplayPort RX instance to DisplayPort TX instance with or without a Pixel Clock Recovery (PCR) module. The below table illustrates design example options available for Agilex™ 7, Stratix® 10, Arria® 10 and Cyclone® 10 GX devices. 2. Design Flow and IP Integration Device Design Example Designation Data Rate Channel Mode Loopback Type Agilex™ 7 DisplayPort SST parallel loopback without PCR DisplayPort SST RBR, HBR, HBR2, HBR3, UHBR10 Simplex Parallel without PCR DisplayPort SST parallel loopback with AXIS Video Interface DisplayPort SST RBR,HBR, HRB2,HBR3, UHBR10 Simplex Parallel with AXIS Video Interface Stratix® 10 DisplayPort SST parallel loopback with PCR (with and without HDCP) DisplayPort SST HBR3, HBR2, HBR, and RBR Simplex Parallel with PCR DisplayPort SST parallel loopback without PCR DisplayPort SST UHBR10 (Stratix 10 H-tile), HBR3, HBR2, HBR, and RBR Simplex Parallel without PCR DisplayPort SST TX-only DisplayPort SST HBR3,HBR2, HBR, RBR Simplex - DisplayPort SST RX-only DisplayPort SST HBR3,HBR2, HBR,RBR Simplex - Arria® 10 DisplayPort SST parallel loopback with PCR (with and without HDCP) DisplayPort SST HBR3, HBR2, HBR, and RBR Simplex Parallel with PCR DisplayPort SST parallel loopback without PCR DisplayPort SST HBR3, HBR2, HBR, and RBR Simplex Parallel without PCR DisplayPort MST parallel loopback with PCR DisplayPort MST HBR3, HBR2, HBR, and RBR Simplex Parallel with PCR DisplayPort MST parallel loopback without PCR DisplayPort MST HBR3, HBR2, HBR, and RBR Simplex Parallel without PCR DisplayPort SST TX-only DisplayPort SST HBR3, HBR2, HBR, and RBR Simplex - DisplayPort SST RX-only DisplayPort SST HBR3, HBR2, HBR, and RBR Simplex - Cyclone® 10 GX DisplayPort SST parallel loopback with PCR DisplayPort SST HBR3, HBR2, HBR, and RBR Simplex Parallel with PCR DisplayPort SST parallel loopback with PCR DisplayPort SST HBR3, HBR2, HBR, and RBR Simplex Parallel without PCR DisplayPort MST parallel loopback with PCR DisplayPort MST HBR3, HBR2, HBR, and RBR Simplex Parallel with PCR DisplayPort MST parallel loopback without PCR DisplayPort MST HBR3, HBR2, HBR, and RBR Simplex Parallel without PCR DisplayPort SST TX-only DisplayPort SST HBR3,HBR2, HBR, RBR Simplex - DisplayPort SST RX-only DisplayPort SST HBR3,HBR2, HBR, RBR Simplex - How do I generate the Quartus® DisplayPort design example? For Agilex™ 7, Agilex™ 5, Stratix®, Arria® 10, and Cyclone® 10 GX devices, use the DisplayPort FPGA parameter editor in the Quartus® Prime Pro Edition software to generate the design example. Click Tools IP Catalog, and select target device family. In the IP Catalog, locate and double-click DisplayPort FPGA IP. The New IP Variation window appears. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named ip. You may select a specific FPGA device in the Device field, or keep the default Quartus® Prime software device selection. Click OK. The parameter editor appears. Configure the desired parameters for both TX and RX. On the Design Example tab, select the design example that fits your criteria. Select Simulation to generate the testbench, and select Synthesis to generate the hardware design example. You must select at least one of these options to generate the design example files. If you select both, the generation time is longer. For Target Development Kit, select the available FPGA development kit. If you select the development kit, then the target device (selected in step 4) changes to match the device on the development kit. Click Generate Example Design. Similarly, the links below provides step-by-step instruction to generate DisplayPort design example from the Quartus® Prime software: DisplayPort Agilex™ 7 F-Tile FPGA IP Design Example User Guide DisplayPort Agilex™ 5 FPGA IP Design Example User Guide DisplayPort Stratix® 10 FPGA IP Design Example User Guide DisplayPort Arria® 10 FPGA IP Design Example User Guide DisplayPort Cyclone® 10 GX FPGA IP Design Example User Guide How do I compile and test my design? For Agilex™ 7 and 10-series devices, the steps to compile and test your DisplayPort design can be found in the following DisplayPort Design Compiling and Testing the Design: Compiling and Testing for Agilex™ 7 F-Tile Compiling and Testing for Agilex™ 5 Compiling and Testing for Stratix® 10 Compiling and Testing for Arria® 10 Compiling and Testing for Cyclone® 10 GX How can I perform DisplayPort functional simulation? For Agilex™ 7, Stratix®, Arria® 10, and Cyclone® 10 GX devices, below are the steps to generate DisplayPort functional simulation: Enable the simulation option in the DisplayPort Parameter Editor and generate DisplayPort design example. Simulating Design: Simulating Design for Agilex™ 7 F-Tile Simulating Design for Agilex™ 5 Simulating Design for Stratix® 10 Simulating Design for Arria® 10 Simulating Design for Cyclone® 10 GX Simulation Testbench: Simulation Testbench for Agilex™ 7 F-Tile Simulation Testbench for Agilex™ 5 Simulation Testbench for Stratix® 10 Simulation Testbench for Arria® 10 Simulation Testbench for Cyclone® 10 GX Where do I find information on the Clock Recovery Core? The Agilex™ 7, Stratix®, Arria® 10, and Cyclone® 10 GX DisplayPort design example uses Pixel Clock Recovery IP. Clock Recovery Core information: DisplayPort IP Core User Guide Where do I find information on the DisplayPort Link Training flow? Before the source device can send video data to sink device, a Link Training process has to be completed between source-sink. DisplayPort Link Training Flow: DisplayPort IP Core User Guide Where do I find information on the DisplayPort API reference and DPCD information? The following resources will provide instructions for the DisplayPort application programming interface (API) reference and DPCD: Source-supported DPCD locations Sink-supported DPCD locations DisplayPort FPGA IP User Guide 3. Board Design and Power Management Pin Connection Guidelines Agilex™ 7 Devices Agilex™ 7 Device Family Pin Connection Guideline: F-Series and I-Series Agilex™ 7 Device Family Pin Connection Guidelines: M-Series Agilex™ 5 Devices Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs Agilex™ 3 Devices Pin Connection Guidelines: Agilex™ 3 FPGAs and SoCs Stratix® 10 Devices Stratix® 10 GX, MX, TX and SX Device Family Pin Connection Guidelines Arria® 10 Devices Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines Cyclone® 10 GX Devices Cyclone® 10 GX Device Family Pin Connection Guidelines Schematic Review Agilex™ 7 Devices Agilex™ 7 Schematic Review Worksheet: F-Series and I-Series Agilex™ 7 Device Schematic Review Worksheet: M-Series Agilex™ 5 Devices Agilex™ 5 Device Schematic Review Worksheet: D-Series and E-Series Agilex™ 3 Devices Agilex™ 3 Device Schematic Review Worksheet Stratix® 10 Devices Stratix® 10 GX, MX, and SX Schematic Review Worksheet Stratix® 10 GX FPGA Development Kit User Guides and Schematics Stratix® 10 SX SoC Development Kit User Guides and Schematics Arria® 10 Devices Arria® 10 GX, GT, and SX Schematic Review Worksheet Arria® 10 GX FPGA Development Kit User Guides and Schematics Arria® 10 SoC Development Kit User Guides and Schematics Cyclone® GX 10 Devices Cyclone® 10 GX Schematic Review Worksheet Cyclone® 10 GX FPGA Development Kit User Guides and Schematics Board Design Guidelines Agilex™ 7 Devices Design Guidelines High-Speed Serial Interface Signal Integrity User Guide Agilex™ 5 PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide PCB Layout, Routing, and Power Distribution Network Design Guidelines: Agilex™ 3 FPGAs and SoCs AN 766: Stratix® 10 High-Speed Signal Interface Layout Design Guidelines User Guide AN 958: Board Design Guidelines Solutions Board Layout Test AN 114: Board Design Guidelines for Programmable Device Packages AN 613: PCB Stackup Design Considerations for FPGAs AN745: Design Guideline for FPGA DisplayPort Interface FMC DisplayPort Daughter Card Revision 8 Schematics FMC DisplayPort Daughter Card Revision 11 Schematics HSMC DisplayPort 1.2 Daughter Card Schematics Disclaimer: The Arria® 10 and Stratix® 10 Development Kit on-board DisplayPort TX board design implementation is NOT recommended as it does not allow PMA PCS bonding. Users are advised to refer to the Bitec design implementation. Power Management AN 910: Agilex™ 7 Power Distribution Network Design Guidelines Agilex™ 7 Power Management User Guide Agilex™ 5 Power Management User Guide Agilex™ 3 Power Management User Guide Stratix® 10 Power Management User Guide Stratix® 10 Early Power Estimator User Guide AN 692: Power Sequencing Considerations for Agilex™ 7, Stratix 10, Arria® 10, and Cyclone® 10 GX Devices Arria® 10 Early Power Estimator User Guide AN 711: Arria® 10 Power Reduction Features Cyclone® 10 Early Power Estimator User Guide Early Power Estimator (EPE) and Power Analyzer AN 750: Using the FPGA PDN Tool to Optimize Your Power Delivery Network Design Device-Specific Power Deliver Network (PDN) Tool 2.0 User Guide AN 721: Creating an FPGA Power Tree Quartus® Prime Pro Edition User Guide Power Analysis and Optimization FPGA Power and Thermal Calculator User Guide Thermal Power Management Agilex™ Devices AN 944: Agilex™ 7 Thermal Modeling with the FPGA Power and Thermal Calculator (PCT) Agilex™ 5 Thermal Design User Guide with the Power and Thermal Calculator (PTC) Agilex™ 3 Thermal Design User Guide Stratix® 10 Devices AN 787: Stratix® 10 Thermal Modeling and Management with the Early Power Estimator AN 943: Stratix® 10 Thermal Modeling with the FPGA Power and Thermal Calculator (PCT) Power Sequencing Agilex™ 7, Stratix® 10, Arria® 10, and Cyclone® 10 GX Devices AN 692: Power Sequencing Considerations for Agilex™ 7, Stratix® 10 Arria® 10, and Cyclone® 10 GX Devices My design require Bitec FMC daughter card. How do I select them? The following table provides a quick guideline in selecting Bitec FMC daughtercard revision. 3. Board Design and Power Management Bitec FMC Daughtercard Revision Supported Data Rate Revision 8 RBR(1.62 Gbps), HBR(2.7 Gbps), HBR2(5.4 Gbps), HBR3(8.1 Gbps), UHBR10 (10 Gbps) Revision 11 RBR(1.62 Gbps), HBR(2.7 Gbps), HBR2(2.7 Gbps), HBR3(8.1 Gbps) Any requirement to use single or dual lanes transceiver channel with Bitec FMC daughter card for 10-series devices? Yes. For DisplayPort design that uses/referred to in an early version of Bitec FMC daughtercard (revision 8 and earlier), the pin assignment in the following link has to be followed at TX and RX due to the lane reversal and polarity inversion at the channel. Device Device Part Number Pin Assignments for Bitec FMC Revision 8 or Earlier Stratix® 10 1SG280HU1F50E2VGS1 DisplayPort Stratix® 10 FPGA IP Design Example User Guide Arria® 10 10AX115S2F45I1SG DisplayPort Arria® 10 FPGA Design Example User Guide Cyclone® 10 GX 10CX220YF780E5G DisplayPort Cyclone® 10 GX FPGA Design Example User Guide How do I create a DisplayPort TX-only or RX-only design? A general guideline to create a DisplayPort TX-only or RX-only design can be found in the DisplayPort Arria® 10 FPGA IP Design Example User Guide . Alternatively, a more detailed explanation specific to the DisplayPort TX-only design can be referred to in the AN 883: Arria® 10 DisplayPort TX-only Design User Guide . 4. Design Examples Arria® 10 Devices AN 793: Arria® 10 DisplayPort 4Kp60 with Video and Image Processing Pipeline Retransmit Reference Design Arria® 10 DisplayPort TX-only Design User Guide Arria® 10 FPGA – DisplayPort Using Onboard Connector (TX Only) Design Example DisplayPort UHD Scaler and Mixer Design Example User Guide AN 900: Arria® 10 DisplayPort 8K RX-only Design. AN 889: 8K DisplayPort Video Format Conversion Design Example 4. Design Examples 5. Debug How do I debug my DisplayPort design? Monitor link training completion status, link rate, and channel count on the development kit on-board user LED. DisplayPort Stratix® 10 FPGA IP Design Example User Guide Monitor video Main Stream Attributes (MSA) information and auxiliary channel traffic of link training via Nios II terminal. DisplayPort FPGA IP User Guide AN 900: Arria® 10 DisplayPort 8K RX-only Design Calculate the required video resolution bandwidth and its recovered clock. DisplayPort Bandwidth & PCR Calculator Translate DisplayPort Link Training AUX Transaction DisplayPort Link Training AUX Translation Tool 5. Debug - 2026-03-10