Is “s2f_cold_reset_reset_n” from Hard Processor System Stratix® 10 FPGA IP active low reset? - Is “s2f_cold_reset_reset_n” from Hard Processor System Stratix® 10 FPGA IP active low reset? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 20.1 and earlier versions, when you enable the “Enable HPS-to-FPGA cold reset output” option in Hard Processor System Intel® Stratix® 10 FPGA IP, a signal “ s2f_cold_reset_reset_n ” is exported in the top level. The reset is not an active low reset but an active high reset. Resolution Please use the " s2f_cold_reset_reset_n " as an active high reset. This problem has been fixed in Intel® Quartus® Prime Pro Edition software version 22.4 and later versions. Custom Fields values: ['novalue'] Troubleshooting 1507927326,22011076422 False ['Hard Processor System Stratix® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.4 19.3 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue'] - 2024-10-27