Should I preserve the unused transmitter pins of an E-Tile Channel PLL on the Intel® Stratix® 10 or the Intel Agilex® 7 E-Tile FPGAs? - Should I preserve the unused transmitter pins of an E-Tile Channel PLL on the Intel® Stratix® 10 or the Intel Agilex® 7 E-Tile FPGAs? Description No, you do not need to preserve the unused transmitter pins of an E-Tile Channel PLL on the Intel® Stratix® 10 or the Intel Agilex® 7 E-Tile FPGAs. Example: If your current design implements an E-Tile Channel PLL in location 4 that clocks E-Tile channels 0-3 in External EMIB Clocking mode, you do not need to preserve the TX pins of channel 4 if that channel were later to be used as a data channel instead of a Channel PLL. Resolution This information will be added to a future revision of the E-Tile Transceiver PHY User Guide. Custom Fields values: ['novalue'] Troubleshooting 18021013013 False ['Stratix® 10 E-Tile Transceiver Native PHY'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.3 21.4 ['Agilex™ 7 FPGA F-Series', 'Stratix® 10 DX FPGA', 'Stratix® 10 MX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']