How do I reconfigure an Arria® 10 FPGA and Cyclone® 10 FPGA I/O PLL with the PLL Reconfig IP when the I/O PLL cannot be locked? - How do I reconfigure an Arria® 10 FPGA and Cyclone® 10 FPGA I/O PLL with the PLL Reconfig IP when the I/O PLL cannot be locked? Description PLL Reconfig IP currently checks the IO PLL lock status before it allows reconfiguration to start. This causes the mgmt_wait_reques t to be asserted until the IO PLL achieves lock. Resolution To work around this problem, edit the .v file shown below in the project IP-generated folder and change the parameter WAIT_FOR_LOCK value from 1 to 0. This will force the PLL Reconfig IP to not check the IOPLL lock status and de-assert the mgmt_waitreques t signal when the core is ready. //synth/altera_pll_reconfig_top.v Custom Fields values: ['novalue'] Troubleshooting 1409616181 False ['IOPLL IP', 'PLL Reconfig IP'] ['FPGA Dev Tools Quartus® Prime Software Pro', 'FPGA Dev Tools Quartus® Prime Software Standard'] novalue 18.1 ['Arria® 10 FPGAs and SoCs', 'Cyclone® 10 FPGAs'] ['novalue'] ['novalue'] ['novalue']