Using Altera® SoC FPGAs: An Introduction - Course Description The focus for this course is to design with Agilex™ 5 SoC FPGAs using the Quartus® Prime software and the software development flow for these devices. It will cover the Hard Processor System (HPS) architecture for Agilex™ 5 SoC FPGAs, including an overview of the Arm* Cortex*-A76 and Arm* Cortex*- A55. You will learn to add and configure the processor component in a Platform Designer system from Quartus® Prime software. You will then learn to implement and configure the first-stage and second-stage bootloaders (based on U-Boot), and how to build and boot to the Linux* OS. You will learn the boot stages for Altera® SoC FPGA devices. At the completion of the course, you will have the knowledge necessary to immediately start using Altera® SoC FPGA devices in your own designs or on development kits. *ARM and AMBA are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. Course Objectives At course completion, you will be able to: Create, manage, and compile an SoC based FPGA using the Platform Designer tool in Quartus Prime Software Compile the first- and second-stage bootloaders, as well as Arm* Trusted Firmware Build a Linux* OS boot image with all the pieces of software Skills Required FPGA knowledge is helpful, but not required Basic knowledge of using the command line in the Linux* OS is helpful, but not required If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_ISOC103. FPGA_ISOC103. <p>Using Altera SoC FPGAs: An Introduction</p>