Why does the Quartus II software not issue a warning message concerning jitter when a PLL is not driven by its dedicated clock input pin for an Arria V device? - Why does the Quartus II software not issue a warning message concerning jitter when a PLL is not driven by its dedicated clock input pin for an Arria V device? Description Due to a bug, current versions of the Quartus® II software will not issue a warning message concerning jitter when a PLL is not driven by its dedicated clock input pin. Resolution The warning that you should receive in the Quartus II software is: Warning (15055): PLL "<PLL Name>" input clock inclk[0] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input This issue is scheduled to be fixed in a future release of Quartus II software. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 12.1 12.0 ['Arria® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']