Why do I receive a fitting error when trying to place the HPS SPI controller clock? - Why do I receive a fitting error when trying to place the HPS SPI controller clock? Description You might receive a fitting error when compiling your Cyclone® V SoC based design if the sclk_out pin associated with the HPS SPI Controller sclk_out pin is assigned to a pin that is not accessible by one of the Regional Clock (RCLK) networks that the sclk_out port on the HPS has access to. Error (14566): Could not place 1 periphery component(s) due to conflicts with existing constraints (1 auto-promoted clock driver(s)) Resolution The HPS SPI controller sclk_out port can access clock networks RCLK[76:81] and RCLK[0:9] . If the sclk_out port needs to access resources outside of these regions, an LCELL primitive must be used to allow other interconnect to be used. Custom Fields values: ['novalue'] Troubleshooting 226208 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] No plan to fix No plan to fix ['Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']