Can I use spread spectrum reference clock (SSC) for External Memory Interfaces Intel® FPGA IP? - Can I use spread spectrum reference clock (SSC) for External Memory Interfaces Intel® FPGA IP? Description Spread Spectrum Clocking is mentioned by JEDEC and our documentation states that the I/O phase-locked loop (PLL) used by the External Memory Interfaces Intel® FPGA IP supports Spread Spectrum Clocking. This may lead you to a conclusion that you can use Spread Spectrum Clocking for the External Memory Interfaces Intel® FPGA IP. Resolution Spread Spectrum Clocking (SSC) is not supported with the External Memory Interfaces Intel® FPGA IP because of the timing closure perspective. Additional Information The External Memory Interfaces Intel® FPGA IP User Gude will be updated with this information. Custom Fields values: ['novalue'] Troubleshooting 18028524851 False ['External Memory Interfaces (EMIF) IP'] ['FPGA Dev Tools Quartus® Prime Software'] novalue No plan to fix ['Agilex™ FPGA Portfolio', 'Arria® 10 Bare Die', 'Cyclone® Bare Die', 'MAX® CPLDs', 'Stratix® FPGAs'] ['novalue'] ['novalue'] ['novalue']