Interfacing Avalon Streaming FIFO IP with GTS Ethernet Hard IP (Agilex 5, quartus v25.3) - Interfacing Avalon Streaming FIFO IP with GTS Ethernet Hard IP (Agilex 5, quartus v25.3) Hello, I posted this question before on the Quartus Prime Forum but saw this forum and thought maybe this would be a better place to post it. Sorry if this is considered spam and not allowed: I want to integrate the Avalon Streaming Single Clock FIFO IP (AVST FIFO IP) with the GTS Ethernet Hard IP (GTS EHIP) , but the GTS EHIP outputs signals rxstatus_valid and rxstatus_data, that don't interface with the AVST FIFO IP. The AVST FIFO IP is in a custom module that sits in between the GTS EHIP and the rest of the 1x10G Ethernet System Example Design: Agilex 5 FPGA E-Series Modular Development Kit (Link: https://altera-fpga.github.io/rel-25.3/embedded-designs/agilex-5/e-series/modular/ethernet/agx5e-ethernet-10g/ug-agx5e-ethernet-10g/). How should I handle these signals? Can I ignore them? Is there a example reference design that does this? Thank you for the help! IP Blocks (left:EHIP, right:avst sc fifo ip): SC FIFO Parameters: Replies: Re: Interfacing Avalon Streaming FIFO IP with GTS Ethernet Hard IP (Agilex 5, quartus v25.3) Hello, I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Altera experts. Otherwise, the community users will continue to help you on this thread. Thank you Chris for supporting!!! Thank you. Replies: Re: Interfacing Avalon Streaming FIFO IP with GTS Ethernet Hard IP (Agilex 5, quartus v25.3) Thank you for the help Chris! I appreciate it, your response is helpful! Replies: Re: Interfacing Avalon Streaming FIFO IP with GTS Ethernet Hard IP (Agilex 5, quartus v25.3) Looking at the design, it doesn't appear the rx_status signals are needed. The routing is just using the IP address. As for start/end of a packet for rx_status, you can use the endofpacket signal from rx_data. Replies: Re: Interfacing Avalon Streaming FIFO IP with GTS Ethernet Hard IP (Agilex 5, quartus v25.3) Hi Chris, Thank you for the reply! A few follow-up questions: 1. Can the rxstatus signals be not connected at all ? I am trying to add on to this design (Design Link: https://altera-fpga.github.io/rel-25.3/embedded-designs/agilex-5/e-series/modular/ethernet/agx5e-ethernet-10g/ug-agx5e-ethernet-10g/) . Will not connecting it cause any system issues? 2. If I uncheck use packets parameter, how does the system figure out start and end of every packet? I am trying to do packet processing. Thank you again Replies: Re: Interfacing Avalon Streaming FIFO IP with GTS Ethernet Hard IP (Agilex 5, quartus v25.3) To interface the rx status and the sc fifo, you should uncheck "use packets" and leave the SC FIFI ready signal unconnected (as the RX side doesn't support backpressure). This means you need to process the frames at datarate. For how to handle this interface, I would take a look at the following section: https://docs.altera.com/r/docs/817676/25.3.1/gts-ethernet-hard-ip-user-guide-agilextm-5-fpgas-and-socs/connect-the-rx-mac-avalon-streaming-client-interface Depending on your application, the rx status may not be required. If you are doing specific processing for VLAN/SLAN, PAUSE/PFC, Control, or Broadcast/Multicast frames, then this would be required.