Why does the F-Tile JESD204C Altera® IP have the j204c_tx/rx_rst_ack_n signals not deassert properly even when tx/rx_rst_n signal has been deasserted and adhered to the F-Tile JESD204C Altera® IP TX/RX Reset Sequence in simulation? - Why does the F-Tile JESD204C Altera® IP have the j204c_tx/rx_rst_ack_n signals not deassert properly even when tx/rx_rst_n signal has been deasserted and adhered to the F-Tile JESD204C Altera® IP TX/RX Reset Sequence in simulation? Description It is observed that the j204c_tx/rx_rst_ack_n acknowledgment reset signals are not deasserting (low -> high) and remain asserted at logic level ‘0’. This behavior is observed even after the user has deasserted the reset signals j204c_tx/rx_rst_n and j204c_tx/rx_rst_avs_n by following the F-Tile JESD204C Altera® IP TX1/RX2 Reset Sequence. There is a Soft Reset Controller (SRC), an internal soft IP module that the F-Tile JESD204C Altera® IP depends on to synchronize the resets across individual lanes in the transceiver. The j204c_tx/rx_rst_ack_n signals depend on this SRC module to determine their proper state. In Quartus® Prime Pro Edition Software version 24.1, FastSIM mode was introduced, speeding up simulation times. As a result, one of the optimizations performed is to speed up the SRC initialization. Due to this, the F-Tile JESD204C Altera® IP did not initialize some internal signals properly in time, as the j204c_tx_avs_clk was provided late. The SRC initialization occurred before the j204c_tx_avs_clk was first toggled. As a result, the j204c_tx/rx_rst_ack_n signal is improperly initialized, leading to improper behavior. Prior to Quartus® Prime Pro Edition Software version 24.1, this issue was not observed because FastSIM was not enabled for the SRC module, and the SRC initialization happens after the j204c_tx_avs_clk starts toggling. Hence, the j204c_tx/rx_rst_ack_n signals de-asserted properly after exiting from reset. This issue affects simulation only and is not observed in hardware. Reference: [1] 5.1.1. F-Tile JESD204C TX Reset Sequence https://www.intel.com/content/www/us/en/docs/programmable/691272/24-1-2-2-0/tx-reset-sequence.html [2] 5.1.2. F-Tile JESD204C RX Reset Sequence https://www.intel.com/content/www/us/en/docs/programmable/691272/24-1-2-2-0/rx-reset-sequence.html Resolution A patch has been released to address this issue for the Quartus® Prime Pro Edition Software version 24.2. This problem is also fixed starting with the Quartus® Prime Pro Edition Software version 24.3. For users who are unable to migrate to the Quartus® Prime Pro Edition Software version 24.2, we recommend the following workaround: Initialize the F-Tile JESD204C Altera® IP in a reset state and ensure that the j204c_tx_avs_clk clock signal is locked. Refer to the following code sample: reconfig_xcvr_reset = '1; j204c_tx_avs_rst_n = '0; j204c_rx_avs_rst_n = '0; j204c_tx_rst_n = '0; j204c_rx_rst_n = '0; Note that the reconfig_xcvr_reset signal is active high while the other reset signals are active low. Once the j204c_tx_avs_clk is locked, users can follow the F-Tile JESD204C TX/RX Reset Sequence to exit out of reset. Ensure that the j204c_tx/rx_rst_ack_n = 0 before exiting out of reset. For more information about this sequence, refer to [1]. To work around this problem in the Quartus® Prime Pro Edition Software version 24.2, install the following patch: quartus-24.2-0.11-patch.zip . This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 24.3. Related Articles Quartus® Prime Pro Edition Software version 24.1 Custom Fields values: ['novalue'] Troubleshooting 14022574261 False ['F-Tile JESD204C IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.3 24.1 ['Agilex™ 7 FPGA F-Series', 'Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['novalue']