Why does the Low Latency Ethernet 10G MAC's dynamic generated 1G/2.5G/10G with 1588 mode example design fail timing in Intel® Stratix® 10 ES1 device? - Why does the Low Latency Ethernet 10G MAC's dynamic generated 1G/2.5G/10G with 1588 mode example design fail timing in Intel® Stratix® 10 ES1 device?
Description Due to a problem in Intel® Quartus® Prime Software version 18.0, the Low Latency Ethernet 10G MAC's dynamic generated 1G/2.5G/10G with 1588 mode example design may fail timing closure. Resolution Launch Design Space Explorer II and perform seed sweep to get best quality of fitter placement as Stratix® 10 FPGA timing model is still at preliminary stage pending engineering characterization.
Custom Fields values:
['novalue']
Troubleshooting
FB: 553657;
True
['Low Latency Ethernet 10G MAC IP']
['FPGA Dev Tools Quartus® Prime Software Pro']
No plan to fix
18.0
['Stratix® 10 FPGAs and SoCs']
['novalue']
['novalue']
['novalue'] - 2023-01-30
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