Why is my Arria V QDR II and QDRII SRAM controller with UniPHY IP missing a CQn clock signal ? - Why is my Arria V QDR II and QDRII SRAM controller with UniPHY IP missing a CQn clock signal ? Description The Arria® V architecture does not support a complementary CQ clock. Instead, both edges of the CQ clock are used to capture the read data. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® V FPGAs and SoCs', 'Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']