Critical Warning: <corename>_if0_p0_pin_map.tcl: Failed to find PLL clock for pins if0|p0|controller_phy_inst|memphy_top_inst|afi_half_clk_reg - Critical Warning: <corename>_if0_p0_pin_map.tcl: Failed to find PLL clock for pins if0|p0|controller_phy_inst|memphy_top_inst|afi_half_clk_reg Description When compiling your DDR2 SDRAM or DDR3 SDRAM UniPHY design in the Quartus® II Software version 11.0 or 11.0SP1, you may experience the following critical warning: Critical Warning: <corename>_if0_p0_pin_map.tcl: Failed to find PLL clock for pins if0|p0|controller_phy_inst|memphy_top_inst|afi_half_clk_reg The critical warning does not occur on the first compile of the design but will occur on all subsequent compiles. The cause of the problem is RAPID_RECOMPILE_MODE set to ON which causes the afi_half_clk_reg to not be preserved in subsequent compiles. Resolution The workaround is to delete the db directory before the design is re-compiled or disable rapid recompile in your project. This issue will be fixed in a future version of the Quartus II software. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 11.0 ['Stratix® III FPGAs', 'Stratix® IV E FPGA', 'Stratix® IV FPGAs', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA'] ['novalue'] ['novalue'] ['novalue']