Serial Lite IP - The Serial Lite FPGA IP core is a simple, low-latency, scalable protocol for high-bandwidth serial data transfer applications. It is suitable for high-bandwidth data communication for chip-to-chip,… Altera, provides leadership programmable solutions that are easy-to-use and deploy in applications from the cloud to the edge, offering limitless AI possibilities. Our end-to-end broad portfolio of… Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE SoC FPGA Cyclone® V ST SoC FPGA Cyclone® V SX SoC FPGA Intel Agilex® 7 FPGAs and SoC FPGAs F-Series Intel Agilex® 7 FPGAs and SoC FPGAs I-Series Intel Agilex® 7 FPGAs and SoC FPGAs M-Series Intel® Cyclone® 10 GX FPGA Intel® Stratix® 10 AX SoC FPGA Intel® Stratix® 10 DX FPGA Intel® Stratix® 10 GX FPGA Intel® Stratix® 10 SX SoC FPGA Intel® Stratix® 10 TX FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA The Serial Lite II FPGA IP core provides a simple and lightweight way to move data from one point to another reliably at high speeds. It consists of a serial link of up to 16 bonded lanes with logic to provide a number of basic and optional link support functions. The Atlantic* interface is the primary access for delivering and receiving data. The Serial Lite II protocol specifies a link that is simple to build, uses as little logic as possible, and requires little work to implement. The Serial Lite II FPGA IP is feature-rich, and can be parameterized through a powerful graphical user interface (GUI). The Serial Lite III IP Core is a simple, low-latency, scalable protocol for high-bandwidth serial data transfer applications. It offers simple connectivity that enables rapid point-to-point data transfers across various transmission media, including printed circuit board (PCB), backplane, copper cabling, and fiber optics. Serial Lite III includes technology-leading transceivers: physical medium attachment (PMA) layer, physical coding sublayer (PCS), and media access control (MAC) layer. The PCS and PMA layers are hardened within Stratix 10, Arria 10, Stratix V, and Arria V FPGAs to save customers valuable FPGA logic resources. The Serial Lite IV IP core also incorporates a MAC, PCS, and PMA block. It supports data transfer up to 58 Gbps per lane with a maximum of 12 PAM4 lanes of the Agilex 7 F-tile General-Purpose Transceivers (FGT), up to 116 Gbps with a maximum of 4 PAM4 lanes of the Agilex 7 F-tile High-Speed Transceivers (FHT) in a single link, up to 28 Gbps per lane with a maximum of 16 non-return-to-zero (NRZ) lanes of FGT, or up to 58 Gbps per lane with a maximum of 4 NRZ lanes of FHT. This protocol offers high bandwidth, low overhead frames, and low I/O count supporting high scalability in both numbers of lanes and speed. The IP is easily reconfigurable with support of a wide range of data rates with Ethernet PCS mode of the E-Tile transceiver and the F-Tile transceiver with our latest GTS transceivers for the Agilex 5 devices. Serial Access Aerospace ASIC Proto Broadcast Data Center Cloud (Public, Private, Hybrid) Data Center OEM (IHV, ISV, SI, VAR) Defense Government Industrial Medical Test Transportation Wireless Serial Lite IP Key Features Serial Lite II: 622 Mbps to 6.375 Gbps per lane. Single or multiple lane support (up to 16 lanes). Full-duplex or self-synchronizing link state machine (LSM). Support for two user packet types: data packet and priority packet Offering Brief No No No Yes Encrypted Verilog Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE SoC FPGA Cyclone® V ST SoC FPGA Cyclone® V SX SoC FPGA Intel Agilex® 7 FPGAs and SoC FPGAs F-Series Intel Agilex® 7 FPGAs and SoC FPGAs I-Series Intel Agilex® 7 FPGAs and SoC FPGAs M-Series Intel® Cyclone® 10 GX FPGA Intel® Stratix® 10 AX SoC FPGA Intel® Stratix® 10 DX FPGA Intel® Stratix® 10 GX FPGA Intel® Stratix® 10 SX SoC FPGA Intel® Stratix® 10 TX FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA Yes Yes Offering Brief Production a1JUi0000049UV3MAM What's Included Encrypted Verilog source code Ordering Information IP-SLITE2; IP-SLITE3/ST; IP-SLITE4 Digikey Mouser a1JUi0000049UV3MAM Production Intellectual Property (IP) a1MUi00000BO8twMAD a1MUi00000BO8twMAD 2025-08-28T18:42:48.000+0000 The Serial Lite FPGA IP core is a simple, low-latency, scalable protocol for high-bandwidth serial data transfer applications. It is suitable for high-bandwidth data communication for chip-to-chip, board-to-board, and backplane applications. The core incorporates a media access control (MAC), physical coding sublayer (PCS), and physical media attachment (PMA) block. Altera Solutions