What is the naming convention for Stratix V IBIS models? - What is the naming convention for Stratix V IBIS models? Description The IBIS model files that are generated by the Quartus® II software for Stratix® V devices do not contain the naming nomenclature for the models within the IBIS model file. The naming nomenclature for the IBIS models is as follows: |Naming Nomenclature All models follow the following naming method <I/O Standard>_<I/O>_<Features> <I/O Standard> refers to: lvttl - 3.3V LVTTL lvcmos - 3.3V LVCMOS 25 - 2.5V LVCMOS 18 - 1.8V LVCMOS 15 - 1.5V LVCMOS 12 - 1.2V LVCMOS hstl18i - 1.8V HSTL Class I hstl15i - 1.5V HSTL Class I hstl12i - 1.2V HSTL Class I hstl18ii - 1.8V HSTL Class II hstl15ii - 1.5V HSTL Class II hstl12ii - 1.2V HSTL Class II sstl2i - 2.5V SSTL Class I sstl18i - 1.8V SSTL Class I sstl15i - 1.5V SSTL Class I sstl2ii - 2.5V SSTL Class II sstl18ii - 1.8V SSTL Class II sstl15ii - 1.5V SSTL Class II sstl135 - 1.35V SSTL sstl125 - 1.25V SSTL hsul12 - 1.2V HSUL lvds - 2.5V LVDS minilvds - 2.5V mini-LVDS rsds - 2.5V RSDS lvpecl25 - 2.5V LVPECL dhstl18i - Differential 1.8V HSTL Class I dhstl15i - Differential 1.5V HSTL Class I dhstl12i - Differential 1.2V HSTL Class I dhstl18ii - Differential 1.8V HSTL Class II dhstl15ii - Differential 1.5V HSTL Class II dhstl12ii - Differential 1.2V HSTL Class II dsstl2i - Differential 2.5V SSTL Class I dsstl18i - Differential 1.8V SSTL Class I dsstl15i - Differential 1.5V SSTL Class I dsstl2ii - Differential 2.5V SSTL Class II dsstl18ii - Differential 1.8V SSTL Class II dsstl15ii - Differential 1.5V SSTL Class II <I/O> refers to: Top & Bottom I/O Bank (Begins with Letter 'c'): crin - Column input, DIFFIO_RX pin ctin - Column input, DIFFIO_TX pin crio - Column I/O, DIFFIO_RX pin ctio - Column I/O, DIFFIO_TX pin <Features> refers to: s0 - Slow Slew Rate s1 - fast Slew Rate d12 - 12mA Current Strength r25 - 25 Ohm series on-chip Termination without Calibration r50c - 50 Ohm series on-chip Termination with Calibration e3r - Emulated LVDS/mini-LVDS/RSDS with 3 external resistors p0 - pre-emphasis disabled p1 - pre-emphasis enabled v0 - low VOD v1 - medium low VOD v2 - medium high VOD v3 - high VOD | Example: lvcmos_crio_d16s3 refers to 3.3V LVCMOS I/O standard with 16mA drive strength, and fast slew rate setting on top and bottom I/O bank | Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']