CPLD constraints - CPLD constraints Where can I get information on locking all the macrocells through SDC file? The constraint editor document I have is talking about doing it through pin planner but like to do it through constraint SDC text file. Replies: Re: CPLD constraints Ganesan, May I know if there is any update? Replies: Re: CPLD constraints Hi Ganesan, I assume locking signal to microcell is probably feature like logic lock region and design partition in Quartus. You can preserve logic there are few method like logic lock, design partition post fit and back annotate. May refer to link below for details https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-design-optimization.pdf https://www.youtube.com/watch?v=XO0Qi_zIpPs Replies: Re: CPLD constraints The best method for doing this is to use a block-based design flow where you divide your design into design partitions and then "lock down" each partition as you complete its optimization. See the block-based design flow user guide: https://www.intel.com/content/www/us/en/programmable/products/design-software/fpga-design/quartus-prime/user-guides.html If you're using Standard instead of Pro, look in the documentation for the "incremental compilation" feature. Replies: Re: CPLD constraints How to lock the routing of some signals to macrocells so build to build the routing does not change. Replies: Re: CPLD constraints The SDC file doesn't lock anything. It just provides timing requirements to the Fitter. I'm not sure what you mean by "locking macrocells".