Error (15065): Clock input port inclk[0] of PLL <PLL instance name> must be driven by a non-inverted input pin or another PLL, optionally through a Clock Control block - Error (15065): Clock input port inclk[0] of PLL <PLL instance name> must be driven by a non-inverted input pin or another PLL, optionally through a Clock Control block Description In the Quartus® Prime Standard Edition Software, you might see this error when the reference clock input of a phase-locked loop (PLL) is connected to the output of the Internal Oscillator IP in the MAX® 10 FPGA devices. Resolution To work around this problem, do not feed the reference clock input of a phase-locked loop (PLL) with the output of the Internal Oscillator IP . Custom Fields values: ['novalue'] Troubleshooting 2205692801 False ['Internal Oscillator IP'] ['FPGA Dev Tools Quartus® Prime Software Standard'] No plan to fix 18.0 ['MAX® 10 10 FPGAs'] ['novalue'] ['novalue'] ['novalue']