For LPDDR3 Interfaces on Arria 10 Devices, all 4 Pairs of CK Pins Must be Reserved - For LPDDR3 Interfaces on Arria 10 Devices, all 4 Pairs of CK Pins Must be Reserved Description For each LPDDR3 interface in your design, you must reserve all four pairs of CK pins, regardless of which pins are required by the design. The CK pins cannot be used for any purpose other than CK. Lanes containing unused CK pins cannot be used as DQ lanes. Unreserved pins can still be used as general purpose I/O pins. Resolution There is no workaround for this limitation. This problem is fixed in version 16.0. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 16.0 15.1 ['Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']