How do I enable autonomous Hard IP in my Arria V or Cyclone V design using Quartus II version 13.1 and earlier? - How do I enable autonomous Hard IP in my Arria V or Cyclone V design using Quartus II version 13.1 and earlier? Description To enable autonomous Hard IP(HIP) in your Arria® V or Cyclone® V design using Quartus® II software version 13.1 and earlier, follow the workaround/fix steps below: Ensure that your device has a die revision capable of autonomous HIP. For detail, refer to the Configuration via Protocol section of your target device Errata Sheet in the following link. http://www.altera.com/literature/lit-es.jsp Resolution Create a quartus.ini file that include the below settings in the INI file. This quartus.ini file should be save in the quartus project directory. If you already have a quartus.ini file, add the below settings to it. PGMIO_ENABLE_AUTONOMOUS_HIP_MODE=ON PGMIO_DISABLE_AV_CV_AUTONOMOUS=OFF Related Articles How do I generate Configuration via Protocol (CvP) programming files for a Arria V or Cyclone V designs? Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 14.0 13.0 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']