Why is the last output frame of the FFT IP core missing EOP? - Why is the last output frame of the FFT IP core missing EOP? Description Due to a problem with the FFT IP core in Quartus® Prime Standard Software version 18.1, you may observe that the last output frame of the FFT IP core is missing EOP when both the Input Order and Output Order are configured to Natural and there are intervals with sink_valid = 0 between input frames. Resolution Configure the Output Order in FFT IP to be Digit Reverse. Custom Fields values: ['novalue'] Troubleshooting 1506795653 False ['FFT IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 18.1 ['Arria® II GX FPGA', 'Arria® II GZ FPGA', 'Arria® V FPGAs and SoCs', 'Cyclone® IV FPGAs', 'Cyclone® V FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Cyclone® 10 FPGAs', 'MAX® 10 10 FPGAs', 'Stratix® 10 FPGAs and SoCs', 'Stratix® IV FPGAs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']