Traffic generator in SerialLite III Streaming IP core design example causes lane sequence error when using burst length of 1. - Traffic generator in SerialLite III Streaming IP core design example causes lane sequence error when using burst length of 1. Description Lane sequence error occurs when burst length is set to 1 in the Traffic Generator module in SerialLite III Streaming IP core hardware testing design example. This impact Stratix V, Arria V GZ, Arria 10, and Stratix 10 devices. Resolution This issue has no workaround. This issue will be fixed in future releases. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 13.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']