Error: RST_N port on the PLL is not properly connected on instance hdmi_tx_top:u_hdmi_tx_top|pll_hdmi:u_iopll_tx|pll_hdmi_altera_iopll_241_5hi4oia:iopll_0|altera_iopll:altera_iopll_i|twentynm_iopll_ip:twentynm_pll|iopll_inst. - Error: RST_N port on the PLL is not properly connected on instance hdmi_tx_top:u_hdmi_tx_top|pll_hdmi:u_iopll_tx|pll_hdmi_altera_iopll_241_5hi4oia:iopll_0|altera_iopll:altera_iopll_i|twentynm_iopll_ip:twentynm_pll|iopll_inst. Description When migrating the HDMI Arria® 10 FPGA IP Design Example from a previous Quartus® Prime Standard Edition that still uses the Nios® II processors to Quartus® Prime Standard Edition version 24.1, you may see the following error during compilation. Error: RST_N port on the PLL is not properly connected on instance hdmi_tx_top:u_hdmi_tx_top|pll_hdmi:u_iopll_tx|pll_hdmi_altera_iopll_241_5hi4oia:iopll_0|altera_iopll:altera_iopll_i|twentynm_iopll_ip:twentynm_pll|iopll_inst. The reset port on the PLL must be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock. Info: Must be connected Resolution The Nios® II Processors are no longer included in the Quartus® Prime Standard Edition version 24.1; it has been discontinued. To workaround this problem, please update the design to use the Nios® V Processor. Custom Fields values: ['novalue'] Troubleshooting 15016474091 False ['HDMI'] ['FPGA Dev Tools Quartus® Prime Software Standard'] No plan to fix 24.1 ['Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']