Why does the Intel® Arria® 10/Cyclone® 10 Hard IP for PCI Express* with Avalon® Memory Mapped (Avalon-MM) DMA interface generated example design encounter fatal error in simulation? - Why does the Intel® Arria® 10/Cyclone® 10 Hard IP for PCI Express* with Avalon® Memory Mapped (Avalon-MM) DMA interface generated example design encounter fatal error in simulation? Description Due to a problem with the Intel® Quartus® Prime software version 19.3 and earlier, you may encounter the above problem when simulating the example design generated from the Intel® Arria® 10/Cyclone® 10 Hard IP for PCI Express* with Avalon® Memory Mapped (Avalon-MM) DMA interface and Gen2 mode in Modelsim* Intel® FPGA Starter Edition. Resolution This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition software version 19.4. Custom Fields values: ['novalue'] Troubleshooting 1507045935 False ['Arria® 10 Cyclone® 10 Hard IP for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro', 'FPGA Dev Tools Quartus® Prime Software Standard'] 19.4 18.0 ['Arria® 10 GT FPGA', 'Arria® 10 GX FPGA', 'Arria® 10 SX FPGA', 'Cyclone® 10 GX FPGA'] ['novalue'] ['novalue'] ['novalue']