UDPIP-10G/25G: 10G/25G UDP/IP Hardware Protocol Stack - Implements a UDP/IP hardware protocol stack enabling high-speed LAN or point-to-point communication and media streaming up to 25 Gbps, even in processor-less SoC designs. Offloads the host CPU from… CAST develops, sells, and supports digital Silicon IP Cores which electronic system designers use to shorten development time and lower production risk. CAST uniquely gives system designers the CAST… Arria® V GT FPGA Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST SoC FPGA Arria® V SX SoC FPGA Cyclone® IV E FPGA Cyclone® IV GX FPGA Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE SoC FPGA Cyclone® V ST SoC FPGA Cyclone® V SX SoC FPGA Intel Agilex® 3 FPGAs and SoC FPGAs C-Series Intel Agilex® 5 FPGAs and SoC FPGAs D-Series Intel Agilex® 5 FPGAs and SoC FPGAs E-Series Intel Agilex® 7 FPGAs and SoC FPGAs F-Series Intel Agilex® 7 FPGAs and SoC FPGAs I-Series Intel Agilex® 7 FPGAs and SoC FPGAs M-Series Intel Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series Intel® Arria® 10 GT FPGA Intel® Arria® 10 GX FPGA Intel® Arria® 10 SX SoC FPGA Intel® Cyclone® 10 GX FPGA Intel® Cyclone® 10 LP FPGA Intel® MAX® 10 FPGA Intel® Stratix® 10 AX SoC FPGA Intel® Stratix® 10 DX FPGA Intel® Stratix® 10 GX FPGA Intel® Stratix® 10 SX SoC FPGA Intel® Stratix® 10 TX FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection. Designed for standalone operation, the core is ideal for offloading the host processor from the demanding task of UDP/IP encapsulation and enables media streaming with speeds up to 25Gbps even in processor-less SoC designs. Trouble-free network operation is ensured through run-time programmability of all the required network parameters (local, destination and gateway IP addresses; UDP ports; and MAC address, etc). The core implements the Address Resolution Protocol (ARP), which is critical for multiple access networks, and the Echo Request and Reply Messages (“ping”) of the Internet Control Message Protocol (ICMP) widely used to test network connectivity. It can use a static IP address or automatically request and acquire an IP address from a Dynamic Host Configuration Server (DHCP) server. Furthermore, the core supports 801.1Q tagging and is suitable for operation in a Virtual LAN. The core is easy to integrate into systems with or without a host processor. Packet data can be read/written to the core via dedicated AMBA® AXI4-stream or Avalon®-ST interfaces, while registers are accessible via an AXI4-Lite, or AHB or Avalon-MM slave interface. Bridges to other interface protocols can be made available upon request. The core is Ethernet MAC-independent but can be made available pre-integrated with a CAST, Altera, AMD, Lattice, Microchip, or other third-party eMAC core." Ethernet Aerospace Broadcast Consumer Data Center Cloud (Public, Private, Hybrid) Data Center OEM (IHV, ISV, SI, VAR) Defense Industrial Medical UDPIP-10G/25G: 10G/25G UDP/IP Hardware Protocol Stack Key Features 10/100/1000, 10G, and 25G Ethernet, IPv4 support without packet fragmentation Offering Brief Yes Yes No Yes Encrypted Verilog Verilog Arria® V GT FPGA Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST SoC FPGA Arria® V SX SoC FPGA Cyclone® IV E FPGA Cyclone® IV GX FPGA Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE SoC FPGA Cyclone® V ST SoC FPGA Cyclone® V SX SoC FPGA Intel Agilex® 3 FPGAs and SoC FPGAs C-Series Intel Agilex® 5 FPGAs and SoC FPGAs D-Series Intel Agilex® 5 FPGAs and SoC FPGAs E-Series Intel Agilex® 7 FPGAs and SoC FPGAs F-Series Intel Agilex® 7 FPGAs and SoC FPGAs I-Series Intel Agilex® 7 FPGAs and SoC FPGAs M-Series Intel Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series Intel® Arria® 10 GT FPGA Intel® Arria® 10 GX FPGA Intel® Arria® 10 SX SoC FPGA Intel® Cyclone® 10 GX FPGA Intel® Cyclone® 10 LP FPGA Intel® MAX® 10 FPGA Intel® Stratix® 10 AX SoC FPGA Intel® Stratix® 10 DX FPGA Intel® Stratix® 10 GX FPGA Intel® Stratix® 10 SX SoC FPGA Intel® Stratix® 10 TX FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA Yes Yes 24.3.1 Offering Brief Production a1JUi0000049U6wMAE What's Included Verilog/System Verilog, Encrypted Verilog/System Verilog, or FPGA netlist Ordering Information UDPIP-1G/10G a1JUi0000049U6wMAE Production Intellectual Property (IP) a1MUi00000BO8rRMAT a1MUi00000BO8rRMAT Member 2025-10-31T21:34:00.000+0000 Implements a UDP/IP hardware protocol stack enabling high-speed LAN or point-to-point communication and media streaming up to 25 Gbps, even in processor-less SoC designs. Offloads the host CPU from UDP/IP encapsulation. All network parameters (IP addresses, UDP ports, MAC) are runtime programmable, supporting static or DHCP-assigned IP. Includes ARP for multi-access networks, ICMP ping for connectivity tests, and IEEE 802.1Q VLAN tagging. Supports up to 32 transmit and 32 receive streaming interfaces (channels), each independently configurable for IP, port, multicast address, and unicast/multicast mode. Integrates easily in SoC designs via AXI4-Stream, Avalon-ST, AHB, AXI, Avalon-MM, or Wishbone interfaces, with data exchange via streaming ports or memory-mapped registers. Ideal for real-time networking, video streaming, and industrial applications requiring low-latency, deterministic UDP/IP communication in FPGA or ASIC designs. Partner Solutions