Why are the clock constraints for ALTPLL incorrect when using derive_pll_clocks? - Why are the clock constraints for ALTPLL incorrect when using derive_pll_clocks? Description Due to a problem in the Quartus® Prime software version 16.0 and 16.0 Update 1, you may see that the phase value is incorrect in the constraints generated by derive_pll_clocks. This occurs when using the ALTPLL IP. Resolution This problem is fixed beginning with the Quartus Prime software version 16.0 Update 2. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 16.0 16.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']