Arria V GZ and Stratix V Hard IP for PCIe IP Core Do Not Cycle through Gen1-Gen3 Data Rates in CBB Testing - Arria V GZ and Stratix V Hard IP for PCIe IP Core Do Not Cycle through Gen1-Gen3 Data Rates in CBB Testing
Description When performing the TX Eye Test as part of the PCI Express Compliance Base Board (CBB) testing, the Arria V GZ and Stratix V Hard IP for PCIe do not cycle through the Gen1, Gen2, and Gen3 data rates. Resolution This issue is fixed in version 13.0 of the Hard IP for PCI Express IP Cores.
Custom Fields values:
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Troubleshooting
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True
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['FPGA Dev Tools Quartus II Software']
13.0
11.0
['Stratix® V FPGAs']
['novalue']
['novalue']
['novalue'] - 2021-08-25
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