Is it possible to dynamically enable or disable Global Clock (GCLK) or Regional clock (RCLK) networks that drive fPLLs in Stratix® V, Arria® V, or Cyclone® V devices? - Is it possible to dynamically enable or disable Global Clock (GCLK) or Regional clock (RCLK) networks that drive fPLLs in Stratix® V, Arria® V, or Cyclone® V devices? Description No, it is not possible to dynamically enable or disable Global Clock (GCLK) or Regional clock (RCLK) networks that drive fPLLs in Stratix® V, Arria® V, or Cyclone® V devices. However, due to a problem in the Quartus® II software version 13.1 and earlier, if you use the enable signal on a clock control block that drives an fPLL, compilation will not fail. Resolution Future versions of the Quartus II software are scheduled to generate an error/warning message when you use the enable signal on a clock control block that drives an fPLL, Custom Fields values: ['novalue'] Troubleshooting 2205824076 False ['PLL'] ['FPGA Dev Tools Quartus II Software'] 14.1 12.0 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']