Why do I see random read errors using DDR2 SDRAM Controller with UniPHY/ DDR3 SDRAM Controller with UniPHY or LPDDR2 SDRAM Controller with UniPHY? - Why do I see random read errors using DDR2 SDRAM Controller with UniPHY/ DDR3 SDRAM Controller with UniPHY or LPDDR2 SDRAM Controller with UniPHY? Description Due to a problem in the Quartus II software version 13.0sp1 and earlier, the output of DQS logic block may cause random read errors. The following configurations may be affected: Arria® V: DDR3 and DDR3L SDRAM designs operating below 450 MHz Arria V: All supported operating frequencies for DDR2/LPDDR2 SDRAM Cyclone® V: All supported operating frequencies for DDR3/DDR3L/DDR2/LPDDR2 SDRAM Resolution This issue has been fixed with the Quartus II software version 13.0sp1 dp5 and later. Related Articles How do I address known software issues for Stratix V, Arria V and Cyclone V devices in the Quartus II software version 13.0 SP1? Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 13.1 12.1.1 ['Arria® V FPGAs and SoCs', 'Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V FPGAs and SoCs', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']