Cyclone V Hard IP for PCI Express IP Core Transmits Incorrect TS1 During Link Training - Cyclone V Hard IP for PCI Express IP Core Transmits Incorrect TS1 During Link Training Description The Cyclone V Hard IP for PCI Express IP Core may send out corrupted TS1 during link training. After sending out corrupted TS1s, the Cyclone V Hard IP for PCI Express IP Core enters the Polling.Config state. However, the link partner can only proceed to the Polling.Active state, causing link training to fail. Resolution This issue is fixed in version 13.1 Update 1 of the Quartus II software. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 13.1.1 11.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']