Mitigating Single Event Upsets in Altera® Arria® 10 and Altera Cyclone® 10 GX Devices - Same Course in Japanese: Arria® 10 デバイスにおける SEU (Single Event Upset) の緩和技法 23 Minutes As cloud-based services continue to grow, protection of that cloud data is even more important, such that single event upsets (SEU) are not just the concern of avionics and safety critical systems. With that in mind, this online training serves as the starting point in understanding Altera® FPGA solutions to detecting, correcting and managing SEU events. In this training, you will start with a brief introduction to SEU and its terms. You then learn the features of the Altera® Arria® 10 and Altera® Cyclone 10 GX device families that can be used in the designing your own SEU mitigation solution. Finally, you will investigate the Advanced SEU Detection (ASD) IP Core to see how you can use this core to even further fine tune your SEU detection and response. Course Objectives At course completion, you will be able to: Enable Altera® Arria® 10 and Altera® Cyclone 10 GX device features to reduce your Failures in Time (FIT) rate and to develop a SEU fault response solution Employ the Advanced SEU Detection (ASD) IP core to improve your fault response by filtering SEU events Skills Required Familiarity with FPGA/CPLD design flow Familiarity with the Altera® Quartus® Prime design software If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OSEUMTGTN. FPGA_OSEUMTGTN. <p>Mitigating Single Event Upsets in Altera Arria 10 and Altera Cyclone 10 GX Devices</p>