Transceiver Reconfiguration Controller IP Core fail min pulse width on av_reconfig_pma_testbus_clk signal - Transceiver Reconfiguration Controller IP Core fail min pulse width on av_reconfig_pma_testbus_clk signal Description This is a known issue and it will be fix in future Quartus ® II release. Resolution Create an external SDC constraint with this constraint and recompile Quartus II project: create_generated_clock -name {av_reconfig_pma_testbus_clk} -source [get_pins -compatibility_mode {*|basic|a5|reg_init[0]|clk}] -divide_by 2 [get_registers {*av_xcvr_reconfig_basic:a5|*alt_xcvr_arbiter:pif*|*grant*}] Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 12.0.1 12.0.2 ['Cyclone® V GT FPGA'] ['novalue'] ['novalue'] ['novalue']