Problem configuring PCIe Endpoint on Stratix10 MX Development Kit - Problem configuring PCIe Endpoint on Stratix10 MX Development Kit I am using the Stratix 10 MX Development Kit. I am using an Example Design I generated in Quartus for “Avalon Memory Mapped (Avalon-MM) Intel Stratix 10 Hard IP+ for PCI Express”. I am using Quartus 19.4 I get this error on programming at about 80% done: Error: Device has stopped receiving configuration data Error message received from device : Device is in configuration state Operation failed Googling finds this workaround: https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/component/2019/error---device-has-stopped-receiving-configuration-data-error-me.html To avoid this error and to enable 3V IOs in a design targeting any variant of Intel Stratix 10 FPGAs, power up the VCCR_GXB and VCCH_GXB rails of the respective transceiver tile as per the Intel Stratix 10 Device Family Pin Connection Guidelines . How is this workaround implemented? Replies: Re: Problem configuring PCIe Endpoint on Stratix10 MX Development Kit Since the issue was resolved, I will set this forum case to close-pending for now. The status will remain in this state for 20 calendar days, simply post a note in this forum and it will be reopened for further investigation. Regards -SK Replies: Re: Problem configuring PCIe Endpoint on Stratix10 MX Development Kit This is silly but there was a problem with the power adapter. After fixing it, the example works. Replies: Re: Problem configuring PCIe Endpoint on Stratix10 MX Development Kit Hi, This is to let you know that we tested 1SM21BHU2F53E1VG with the Avalon-MM design that generated from the PCIe GUI. It is working fine. The 1SM21BHU2F53E2VGS1 is the engineering sample device, and this board is currently not available for testing. When you generate the example design from the PCIe IP AVMM GUI, did you select "Stratix 10 MX H-Tile ES1 FPGA Development Kit"? Regards -SK Replies: Re: Problem configuring PCIe Endpoint on Stratix10 MX Development Kit I would appreciate a reference example that works using the Stratix MX using Avalon Memory Mapped (Avalon-MM) Intel Stratix 10 Hard IP+ for PCI Express”. The part number is 1SM21BHU2F53E2VGS1. I am using the SMX Kit listed on this page: https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-s10-mx.html Replies: Re: Problem configuring PCIe Endpoint on Stratix10 MX Development Kit Please find attached my qsf file. Could somebody also please double-check the refclk and perst assignments?